For a semiconductor device, as the integration level is increased by reducing the size of the circuit elements and as the voltage of the power source is reduced, erroneous operation due to noise becomes a serious problem. Power supply noise caused by variations in the power source potential or ground potential is particularly troublesome.
In recent years, there has been a tendency to increase the number of bits (.times.4 configuration, .times.8 configuration, .times.16 configuration, etc.) in a dynamic random access memory (DRAM), which is a type of a semiconductor memory device. As the number of bits is increased, the number of input and output buffers for performing input/output of the data is increased. Since there is a large current flowing during switching (logic variation) of the output buffer, when data is output in a multiple-bit DRAM, a very large current flows into the semiconductor chip through the lead frame, or a very large current flows from the semiconductor chip. Since there is a parasitic inductance present in the lead frame, when a large current flows in the lead frame, a back electromotive force of the aforementioned parasitic inductance causes a variation in the ground potential. This variation in the power source potential or ground potential is the power source noise.
The circuit portion that is most susceptible to the influence of the power source noise is the input buffer, which may exhibit faulty operation due to power source noise. In the conventional DRAM, the following measures are taken to suppress the influence of power source noise.
(1) A differential amplifier, etc., is used in the input buffer to increase the noise resistance of the input. PA0 (2) More power source pins and ground pins are arranged to reduce power source noise. PA0 (3) By distributing the power source wiring of the input buffer in the semiconductor chip (here, the power source wiring refers to both the wiring for the power source potential and the wiring for the ground potential) to the output buffer and other circuits' power source wiring, the power source noise due to overlap with the power source wiring of the input buffer can be reduced.
However, for an LSI (large scale integration) circuit with a high integration level, there is a tendency to decrease the power source voltage from 5 V to 3.3 V. As the power source voltage is decreased, the proportion of the noise of the same magnitude becomes larger. Consequently, the influence of the power source noise on the input buffer is increased. Also, in order to realize a high speed of operation, a high current is needed for driving. This increase in the driving current is also a reason for the increase in power source noise.
Factors that influence power source noise have been modeled. The results indicate that in addition to the transfer from the lead frame, as considered in the past, the transfer from the semiconductor substrate is also significant. Since a large current flows in the semiconductor chip, the potential of the semiconductor substrate varies, and this variation in the potential of the substrate couples to the power source wiring via the parasitic inductance between the semiconductor substrate and the power source wiring (for both the potential of the power source and the potential of the ground), and the power source noise transferred from the semiconductor substrate takes place due to this overlap. Usually, as the power source wiring is connected to the circuit on the semiconductor substrate, there is a significant coupling impedance between the power source wiring and the semiconductor substrate due to the junction capacitance and mutual inductance. For the aforementioned conventional means for suppressing the power source noise, only the power source noise transferred from the lead frame is taken into consideration; hence, the power source noise transferred from the semiconductor substrate cannot be prevented. This is a problem. Also, variation in the semiconductor substrate potential may be transferred directly to the circuit elements as noise, causing erroneous operation. This is also a problem.
For the semiconductor device, due to operation of the internal circuit arranged on the semiconductor chip, current flow from/to the semiconductor chip through the lead frame increases. Due to the increased current, there is a variation in the potential of the semiconductor substrate of the semiconductor chip; the noise caused by this variation in the potential is transferred to the power source wiring or circuit elements of the semiconductor chip, causing erroneous operation of the circuit.